Design of Hardware Transactional Memory for Usage in Embedded Systems
Transactional Memory applies optimistic synchronization to increase parallelism and therefore execution performance on multi-core processors. Moreover, Transactional Memory simplifies programmability of parallel applications by its deadlock avoidance. While Hardware Transactional Memory is available in current desktop and server processors as e.g. Intel Haswell or IBM BlueGene/Q- and Power8 processors, implementations for embedded processors do not exist despite further beneficial properties: avoidance of priority inversion and support of fault-tolerant execution.
Target of this project is to investigate the deployment of Transactional Memory in embedded systems. We will design a Hardware Transactional Memory and investigate its integration in a current embedded multi-core simulator. The following aspects will be systematically investigated: (1) support of real-time capable transactions, (2) optimistic synchronization of parallel tasks, (3) transaction management control for embedded systems, and (4) fault-tolerant execution by exploiting the checkpointing ability of Transactional Memory.