Hardware Complexity of Processors

Hardware Complexity of Processors

  • Start date: 01.01.1999
  • End date: 31.12.2001
  • Funded by: Universität Augsburg
  • Local head of project: Prof. Dr. Theo Ungerer



In cooperation with Mateo Valero and Josep L. Larriba-Pey of Departament d'Arquitectura de Computadors, UPC, Baecelona, Spain, and with Reiner Kolla of Department of Computer Science, University of Würzburg, Germany.


Our target is to set performance in comparison with the number of transistors and the chip-space required to implement the simulated features. We supplemented the SimpleScalar Toolset as well as our own SMT processor simulator by a tool that estimates transistor count and chip space requirements of the simulated features. The tool is based on Microsoft Excel.


To estimate the chip space and the amount of transistors we use an analytical method for memory-based structures like register files or internal queues and an empirical method for logic blocks like control logic and functional units. For the analytical method we calculate the amount of bit cells, which are needed for the memory-based structures and the number of ports to access them. Based on this information, we calculate the number of transistors, assuming four transistors to implement a basic bit cell, two transistors per write port and one transistor per read port.


To calculate the chip-space of a memory based structure we estimate the area of a basic cell. The basic area of a bit cell is increased in height and width by the number of the ports. We use the information of a basic bit cell space and the number of the ports to calculate its area, from that we are able to estimate the whole chip-space. To be independent of chip technology we apply the half-feature size l as measure of length, e.g., 1 mm2 in 0.5 micron technology equals 16 million l2. For the non memory-based parts of the processor we measure the floor plans of existing processors. With this empirical approach we estimate the sizes of the basic logic blocks of the processors. Using this data, we calculate the necessary chip space of the logic blocks.


To estimate the transistor amount of hypothetical processors with our tool, we calculate the average transistor density of non memory-based structures of real processors by measuring floor plans (SPARC64 and HP PA-8000) and by additional information about the transistor amount of the measured logic blocks. We validated the tool by estimating the PowerPC 604 configuration and reached the same 3.6 million transistor count and nearly the same die size as the real processor.


The SimpleScalar directed estimation tool is now available to the general public (April 18, 2001):

The Karlsruhe Simultaneous Multithreaded Simulator directed estimation tool version is also available (April 18, 2001):





  • Transistor Count and Chip-Space Estimation of SimpleScalar-based Microprocessor Models
    Steinhaus Marc, Kolla Reiner, Larriba-Pey Josep L., Ungerer Theo, Valero Mateo
    Workshop on Complexity-Effective Design, June 30, 2001, in conjunction with the 28th International Symposium on Computer Architecture June 30 - July 4, 2001, Göteborg, Sweden


  • Transistor Count and Chip-Space Estimation of Simulated Microprocessors
    M. Steinhaus, R. Kolla, J. L. Larriba-Pey, Th. Ungerer, M. Valero
    Submitted for publication, available as Research report UPC-DAC-2001-16, UPC, Barcelona, Spain




  • On Performance, Transistor Count and Chip Space Assessment of Multimedia-enhanced Simultaneous Multithreaded Processors
    Ulrich Sigmund, Marc Steinhaus, Theo Ungerer
    Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC-4), Monterrey, Ca., Dec. 10, 2000