Many-Core Simulator

Start date:  01.01.2014


Funded by:  Universität Augsburg


Local head of project:  Prof. Dr. Theo Ungerer


Local scientists:  Jörg Mische


Publications:  publication list


MacSim is a cycle-accurate simulator for real-time many-core processors with a large number of cores.


It simulates embedded real-time systems, where a predictable execution time, high performance and small energy consumption are the predominant requirements. To meet these requirements, many simple and energy-efficient processing cores are connected by a real-time network (real-time NoC). By specialising to such architectures, the simulation can be tremendously accelerated, enabling the cycle-accurate simulation of architectures with large core numbers.


Unlike other many-core simulators, only simple in-order cores are supported. Chip area intensive techniques like out-of-order execution, speculative branch prediction, shared memory and a complex memory hierarchy with multiple cache stages requiring a coherence protocol are explicitly avoided.


Simple cores increase the execution time per core, but due to the smaller area demand more cores fit on one chip. Furthermore small cores are more energy-efficient and the worst case execution time (WCET) analysis is simplified. Therefore this architecture model particularly suits the above mentioned requirements of embedded systems, where chip area, energy consumption and real-time capability are more important than sequential execution time.


As only network messages allow an interaction between cores, a single core can be simulated fast, exact and relatively independent of the other cores, providing high simulation speed. Restriction to real-time capable algorithms for communication further speed up the simulation, because real-time networks are less dynamic than standard networks, collisions are widely avoided and communication times can be statically fixed.


MacSim's aim is to achieve a cycle-accurate simulation that is identical to the real execution times of a real many core implemented in an FPGA.