Multi-Core Response Time Analysis (MRTA)
|Local Head of Project
|Prof. Dr. Sebastian Altmeyer
In our everyday life, we interact with a huge number of computer systems embedded into larger devices. Examples are phones, cars, fridges, air-planes and many more. Many of these devices are safety-critical real-time systems. Real-time means that the correctness of a system is not only a functional (the right result), but also an extra-functional property (the right result at the right time). Safety-critical means that a single failure—such as a wrong timing—may lead to a catastrophe and the loss of life: An airbag controller, for instance, has not only to decide whether or not to inflate the airbag, but has to do so before the driver’s head hits the steering wheel. Safety-critical real-time systems thus undergo a thorough timing verification to fulfil highest validation requirements. Timing verification is traditionally a two-step process. The execution time of each individual software task is derived independently and then given to the schedulability analysis, which analyses the combination of the tasks on the system. While this timing verification is valid for state-of-the-art embedded processors, it fails for modern multi-core systems optimized towards the average-case and high-performance computing. Due to interferences on shared resources (bus, cache, etc.), the timing of an individual task highly depends on the tasks running in parallel on the other cores and cannot be analysed independently anymore. Multi-core architectures, however, are the only viable solution to accommodate performance demands of modern computer systems in general and of modern embedded real-time systems in particular. In this project, we will develop a timing verification for real-time multi-cores. Interference on shared resources will be modelled explicitly and reflected in the task model, i.e., in the parameters de- scribing the tasks’ timing behaviour. Theoretical schedulability results—valid for the obsolete model—will be put to a test and updated for the interference-aware task model.